A buck-boost voltage converter receives an unregulated input voltage and generates an increased or decreased regulated output voltage, where the target output voltage is set by component values in a feedback circuit. The buck-boost converters related to the present inventor are pulse-width modulation (PWM) converters, where the switching duty cycle of either buck or boost mode transistor switches controls the output voltage. The switching causes current through a smoothing inductor to ramp up and down as the inductor is charging and discharging.
FIG. 1 is a simplified schematic diagram of the switching, feedback, and filtering components used by both a prior art PWM buck-boost converter and one embodiment of the inventive PWM buck-boost converter. As shown in FIG. 1, a single inductor buck-boost converter 10 typically consists of four switches arranged in a bridge configuration. Switches SW1 and SW2 form one pair, often referred to as the buck switches, while switches SW3 and SW4 form a second pair often referred to as the boost switches. Switch SW2 is sometimes called a recirculating switch.
Switches SW1 and SW2 (as well as SW3 and SW4) are mutually exclusive so, when switch SW1 is on, switch SW2 is off and vice versa. The same applies to switches SW3 and SW4.
Between these two sets of switch pairs is the inductor L. Capacitor C0 filters the ramping inductor current and provides a relatively constant output voltage Vout. Capacitor C1 filters current signals generated by the error amplifier 12 and creates an error voltage Ve.
Considering the case of fixed frequency operation, the proportion of time for which switch SW1 is closed is called the buck duty cycle and, similarly, the proportion of time for which switch SW3 is closed is called the boost duty cycle. The duty cycles for the buck and boost switch pairs are controlled independently.
The buck-boost converter 10 controls the buck and the boost duty cycles in order to maintain a constant output voltage for a given input voltage Vin. At the desired output voltage Vout, the divided voltage between the resistors R1 and R2 approximately equals the reference voltage Vref applied to the error amplifier 12 (a transconductance amplifier). The resistors R3 and R4 set the gain of the error amplifier 12. The filtered output of the error amplifier 12 (the error voltage Ve) is compared to buck and boost sawtooth waveforms, and the time of crossing within the cycle controls the duty cycle of the buck or boost switches to maintain the output voltage Vout at the desired level. Although the sawtooth frequency is typically greater than 1 MHz, the voltage feedback loop is a relatively slow loop since the output voltage is highly filtered and is slow to change.
The comparators are part of a PWM controller (not shown in FIG. 1) that outputs pulses to buck and boost gate drivers 16 and 18 so that the proper switches are fully switched on and off and there is no overlap in the on-states.
If we assume a fixed output voltage, and a slowly falling input voltage (e.g., from a battery) we can start to examine the problems with prior art buck-boost converters.
When the input voltage Vin is high, then the buck-boost converter 10 functions in buck mode, with switches SW1 and SW2 switching every cycle and with switch SW4 permanently closed (and hence switch SW3 permanently open).
As the input voltage Vin continues to fall, switch SW1 is on for a longer and longer proportion of each cycle, and switch SW2 is on for less and less of each cycle. At some point, switch SW1 can no longer turn off fully at the end of each cycle (and switch SW2 can no longer turn on fully) and, if nothing was done, the fixed frequency repetitive nature of the converter operation would be broken, and a series of pulses would ensue, where switch SW1 would be on for 100% of some cycles and less than 100% for others.
This non-repetitive nature in the buck mode, at a time when the input voltage approximately equals the output voltage, would cause the inductor current and output voltage ripple to undesirably increase if nothing were done about it.
A buck-boost mode is a mode which is commonly used when the output voltage Vout is close to the input voltage Vin. In this mode, all four switches operate as two independently controlled pairs of mutually exclusive switches.
In this mode, it is the relative time between switches SW3 and SW2 being on that causes the inductor current (and hence the output voltage) to have increased or decreased over a whole cycle.
In a pure boost mode, switch SW1 is permanently on, and SW2 is permanently off. As the input voltage Vin falls, then for a fixed output voltage, switch SW3 comes on for longer proportions of the switching period (and hence SW4 comes on less of the switching period). In a similar way to the buck mode, the boost mode is limited by the minimum time for which SW3 can come on. If the input to output voltage ratio then demands a yet smaller time for SW3 to come on, then a repetitive fixed frequency operation would be broken and SW3 would be completely off for some periods and on for others, and the inductor current and output voltage ripple would undesirably increase.
At first glance, it would seem that with a combination of buck mode, buck-boost mode, and boost mode any combination of input and output voltages can be accommodated and a fixed frequency repetitive operation could be maintained, and indeed this is the theoretical case. However, in existing buck-boost converters, the transitions between modes result in small glitches in the output voltage Vout due to the lack of a constant, repetitive, fixed frequency operation of the converter.
This glitch occurs as follows. Let's assume a converter initially operating with an input voltage Vin much higher than the output voltage Vout and operating in buck mode, and then consider what happens as we drop the input voltage Vin while maintaining a constant output voltage Vout.
In the buck mode, the rate of rise of inductor current in one cycle is related to the input voltage Vin minus the output voltage Vout, while the rate of decay of inductor current is proportional to the output voltage Vout. For stable operation, the inductor current decays to the same level at the end of a cycle as that level which started the cycle. This is shown in the graph 20 of FIG. 2. The slopes of each inductor current waveform segment are given in FIG. 2, corresponding to a particular combination of switches being on. The voltage Vin across the inductor corresponds to switches SW1 and SW3 being on. The voltage Vin-Vout across the inductor corresponds to switches SW1 and SW4 being on. And the voltage Vout across the inductor corresponds to switches SW2 and SW4 being on.
If we now consider that this stable buck mode operation of graph 20 is just on the mode transition limit, where the turn off time of switch SW1 cannot be reduced any further, and then the input voltage Vin drops still further, we would want to go into the buck-boost mode. The transition into the buck-boost mode occurs when the input voltage Vin is slightly greater than the output voltage Vout because there is a small voltage drop in the converter.
Graph 22 shows the buck-boost mode that would result if we did nothing more than introduce a minimum boost pulse at the start of each buck-boost cycle when the converter just transitioned into the buck-boost mode. At the start of the buck-boost mode, when the input voltage has fallen to slightly greater than the output voltage, the buck mode continues to operate at its maximum duty cycle, so switch SW2 turns on for a minimum time at the end of each cycle. Also, at the start of the buck-boost mode, the boost switch SW3 turns on for the minimum time (in the minimum boost duty cycle).
In graph 22, we can see that because of the minimum boost pulse the minimum turn on-time of switch SW3 is insufficiently small to create the slight boost needed to regulate the output voltage, so the inductor current cannot return to where it started the cycle and, as a result, the voltage control loop would cause the control signal to oscillate, choosing only some buck cycles and some buck-boost cycles for switching, in order to try to make the output voltage Vout be the desired regulated voltage. When the output voltage becomes too high, the buck mode would then be initiated (due to a lowering of the error voltage Ve in FIG. 1) in an attempt to lower the output voltage to the desired level, followed by the buck-boost mode being initiated after the output voltage falls too low. This oscillating behavior between modes is seen on many of the products on the market today.
If the input voltage Vin falls further, while maintaining a constant output voltage, the inductor current will fall more rapidly, but rise more slowly (at least during the Vin-Vout portion). Eventually the inductor current will be able to fall to the same level at which it started the cycle, and stable buck-boost operation will be possible.
As the input voltage Vin drops further, Vin-Vout will become negative and finally get to a point where we would want to remove the buck recirculation period (the Vout/L) period, to keep switch SW2 off, and go to the boost mode.
If the converter is at the border between buck-boost mode and boost mode, we can see that simply removing the buck recirculation period would once again result in the inductor current not being able to return at the end of a cycle to the point where it started the cycle. Again this would result in the output voltage and control loop jumping between buck-boost and boost mode pulses, in order to try and maintain the same average voltage.
Eventually, with the input voltage Vin falling still further, a stable boost mode operation would be obtained.
This unsatisfactory situation is the state of many of the buck-boost chips on the market.
What is needed is a technique to provide smoother transitions into and out of the buck-boost mode in a buck-boost converter.